可訂購部件
| 型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經銷商處購買 |
|---|---|---|---|---|
| 74AUP1T98GW-Q100 | 74AUP1T98GW-Q100H | 935303992125 | SOT363-2 | 訂單產品 |
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Click here for more information74AUP1T98GW-Q100
Low-power configurable gate with voltage-level translator
The 74AUP1T98?-?Q100 is a configurable multiple function gate with level translating, Schmitt?-?trigger inputs. The device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3?-?bit input. All inputs can be connected directly to VCC or GND. Low threshold Schmitt trigger inputs allow these devices to be driven by 1.8 V logic levels in 3.3 V applications.
This device ensures very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 2.3 V to 3.6 V
CMOS low power dissipation
High noise immunity
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Complies with JEDEC standards
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
Low static power consumption; ICC = 1.5 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Overvoltage tolerant inputs to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
參數類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Package name |
|---|---|---|---|---|---|---|---|---|---|
| 74AUP1T98GW-Q100 | 2.3?-?3.6 | CMOS | ± 1.9 | 3.9 | 70 | 1 | ultra low | -40~125 | TSSOP6 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AUP1T98GW-Q100 | 74AUP1T98GW-Q100H (935303992125) |
Active | aR |
TSSOP6 (SOT363-2) |
SOT363-2 | SOT363-2_125 |
環(huán)境信息
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AUP1T98GW-Q100 | 74AUP1T98GW-Q100H | 74AUP1T98GW-Q100 |
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Series
文檔 (8)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74AUP1T98_Q100 | Low-power configurable gate with voltage-level translator | Data sheet | 2023-07-17 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| SOT363-2 | 3D model for products with SOT363-2 package | Design support | 2023-02-02 |
| aup1t98 | aup1t98 IBIS model | IBIS model | 2014-12-21 |
| Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Leaflet | 2019-04-12 |
| SOT363-2 | plastic thin shrink small outline package; 6 leads; body width 1.25 mm | Package information | 2022-11-21 |
| SOT363-2_125 | TSSOP6 ; Reel pack for SMD, 7"; Q3/T4 product orientation | Packing information | 2022-11-04 |
| 74AUP1T98GW-Q100_Nexperia_Product_Reliability | 74AUP1T98GW-Q100 Nexperia Product Reliability | Quality document | 2024-06-16 |
訂購、定價與供貨
| 型號 | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74AUP1T98GW-Q100 | 74AUP1T98GW-Q100H | 935303992125 | Active | SOT363-2_125 | 3,000 | 訂單產品 |
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74AUP1T98GW-Q100
Low-power configurable gate with voltage-level translator
從安世半導體購買
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