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Click here for more information74LVT02DB
3.3 V Quad 2-input NOR gate
The 74LVT02 is a quad 2?-?input NOR gate. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Alternatives
Features and benefits
Wide supply voltage range from 2.7 V to 3.6 V
Output capability: +64 mA and -32 mA
Direct interface with TTL levels
Overvoltage tolerant inputs to 5.5 V
Power-up 3-state
No bus current loading when output is tied to 5 V bus
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 500 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
JESD8C (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to 85 °C
PCB Symbol, Footprint and 3D Model
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封裝
下表中的所有產品型號均已停產 。
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVT02DB | 74LVT02DB,112 (935208960112) |
Obsolete | no package information | ||||
| 74LVT02DB,118 (935208960118) |
Obsolete | ||||||
環(huán)境信息
下表中的所有產品型號均已停產 。
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVT02DB | 74LVT02DB,112 | 74LVT02DB |
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| 74LVT02DB | 74LVT02DB,118 | 74LVT02DB |
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.