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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調節(jié)ESD保護

MOSFET

氮化鎵場效應晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應用認證產(chǎn)品(AEC-Q100/Q101)

74AUP1T58GW

Low-power configurable gate with voltage-level translator

The 74AUP1T58 is a configurable multiple function gate with level translating, Schmitt-trigger inputs. The device can be configured as any of the following logic functions AND, OR, NAND, NOR, XOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. Low threshold Schmitt trigger inputs allow these devices to be driven by 1.8 V logic levels in 3.3 V applications.

This device ensures very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 2.3 V to 3.6 V

  • High noise immunity

  • Low static power consumption; ICC = 1.5 μA (maximum)

  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

  • Overvoltage tolerant inputs to 3.6 V

  • Low noise overshoot and undershoot < 10 % of VCC

  • IOFF circuitry provides partial power-down mode operation

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

參數(shù)類型

型號 VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) fmax (MHz) Nr of bits Power dissipation considerations Tamb (°C) Package name
74AUP1T58GW 2.3?-?3.6 CMOS ± 4 3.9 70 1 ultra low -40~125 TSSOP6

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

型號 可訂購的器件編號,(訂購碼(12NC)) 狀態(tài) 標示 封裝 外形圖 回流焊/波峰焊 包裝
74AUP1T58GW 74AUP1T58GW,125
(935280466125)
Active a8 SOT363-2
TSSOP6
(SOT363-2)
SOT363-2 SOT363-2_125

環(huán)境信息

型號 可訂購的器件編號 化學成分 RoHS RHF指示符
74AUP1T58GW 74AUP1T58GW,125 74AUP1T58GW rohs rhf rhf
品質及可靠性免責聲明

文檔 (8)

文件名稱 標題 類型 日期
74AUP1T58 Low-power configurable gate with voltage-level translator Data sheet 2023-07-26
AN10161 PicoGate Logic footprints Application note 2002-10-29
SOT363-2 3D model for products with SOT363-2 package Design support 2023-02-02
aup1t58 aup1t58 IBIS model IBIS model 2014-12-21
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Leaflet 2019-04-12
SOT363-2 plastic thin shrink small outline package; 6 leads; body width 1.25 mm Package information 2022-11-21
SOT363-2_125 TSSOP6 ; Reel pack for SMD, 7"; Q3/T4 product orientation Packing information 2022-11-04
74AUP1T58GW_Nexperia_Product_Reliability 74AUP1T58GW Nexperia Product Reliability Quality document 2024-06-16

支持

如果您需要設計/技術支持,請告知我們并填寫 應答表 我們會盡快回復您。

模型

文件名稱 標題 類型 日期
aup1t58 aup1t58 IBIS model IBIS model 2014-12-21
SOT363-2 3D model for products with SOT363-2 package Design support 2023-02-02

PCB Symbol, Footprint and 3D Model

Model Name 描述

訂購、定價與供貨

型號 Orderable part number Ordering code (12NC) 狀態(tài) 包裝 Packing Quantity 在線購買
74AUP1T58GW 74AUP1T58GW,125 935280466125 Active SOT363-2_125 3,000 訂單產(chǎn)品

樣品

作為 Nexperia 的客戶,您可以通過我們的銷售機構訂購樣品。

如果您沒有 Nexperia 的直接賬戶,我們的全球和地區(qū)分銷商網(wǎng)絡可為您提供 Nexperia 樣品支持。查看官方經(jīng)銷商列表

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

可訂購部件

型號 可訂購的器件編號 訂購代碼(12NC) 封裝 從經(jīng)銷商處購買
74AUP1T58GW 74AUP1T58GW,125 935280466125 SOT363-2 訂單產(chǎn)品
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