可訂購部件
| 型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經銷商處購買 |
|---|---|---|---|---|
| 74LVT16543ADGG | 74LVT16543ADGG,118 | 935203040118 | SOT364-1 | 訂單產品 |
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Click here for more information74LVT16543ADGG
3.3 V 16-bit registered transceiver; 3-state
The 74LVT16543A is a 16?-?bit registered transceiver with 3?-?state outputs. The device can be used as two 8?-?bit transceivers or one 16?-?bit transceiver.
Data flow in each direction is controlled by intput enable (nEAB and nEBA), latch enable (nLEAB and nLEBA), and output enable (nOEAB and nOEBA) inputs. For A to B data flow, the device operates in the transparent mode when (nEAB) and (nLEAB) are LOW. A subsequent LOW?-?to?-?HIGH transition of the nLEAB input latches the data and the outputs no longer change with the inputs. A HIGH on either nEAB or nOEAB causes the outputs to assume a high?-?impedance OFF?-?state.
Control of data flow from B to A is similar, but using the nEBA, nLEBA, and nOEBA inputs. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs
Features and benefits
16-bit universal bus interface
3-state buffers
Wide supply voltage range from 2.7 V to 3.6 V
Input and output interface capability to systems at 5 V supply
Overvoltage tolerant inputs to 5.5 V
Direct interface with TTL levels
BiCMOS high speed and output drive
Output capability: +64 mA/-32 mA
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
Live insertion/extraction permitted
Power-up 3-state
Power-up reset
No bus current loading when output is tied to 5 V bus
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 500 mA per JESD 78 Class II Level B
Complies with JEDEC standards
JESD8C (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C
參數類型
| 型號 | VCC(A) (V) | VCC(B) (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Nr of bits | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|
| 74LVT16543ADGG | n.a. | n.a. | TTL | -32/64 | 2.2 | 16 | 150 | medium | -40~85 | TSSOP56 |
封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVT16543ADGG | 74LVT16543ADGG,118 (935203040118) |
Active | LVT16543A |
TSSOP56 (SOT364-1) |
SOT364-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT364-1_118 |
Series
文檔 (9)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74LVT16543A | 3.3 V 16-bit registered transceiver; 3-state | Data sheet | 2024-07-08 |
| SOT364-1 | 3D model for products with SOT364-1 package | Design support | 2020-01-22 |
| lvt16543a | lvt16543a IBIS model | IBIS model | 2013-04-09 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| SOT364-1 | plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm body | Package information | 2022-06-23 |
| SOT364-1_118 | TSSOP56; Reel pack for SMD, 13"; Q1/T1 product orientation | Packing information | 2020-04-21 |
| 74LVT16543ADGG_Nexperia_Product_Reliability | 74LVT16543ADGG Nexperia Product Reliability | Quality document | 2024-06-16 |
| lvt16 | lvt16 Spice model | SPICE model | 2013-05-07 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
支持
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訂購、定價與供貨
| 型號 | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74LVT16543ADGG | 74LVT16543ADGG,118 | 935203040118 | Active | SOT364-1_118 | 2,000 | 訂單產品 |
樣品
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74LVT16543ADGG
3.3 V 16-bit registered transceiver; 3-state
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