可訂購(gòu)部件
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 訂購(gòu)代碼(12NC) | 封裝 | 從經(jīng)銷(xiāo)商處購(gòu)買(mǎi) |
|---|---|---|---|---|
| 74HC573PW-Q100 | 74HC573PW-Q100,118 | 935298865118 | SOT360-1 | 訂單產(chǎn)品 |
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Click here for more information74HC573PW-Q100
Octal D-type transparent latch; 3-state
The 74HC573-Q100; 74HCT573-Q100 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
- Wide supply voltage range from 2.0 V to 6.0 V
- CMOS low power dissipation
- High noise immunity
Input levels:
For 74HC573-Q100: CMOS level
For 74HCT573-Q100: TTL level
Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
Useful as input or output port for microprocessors and microcomputers
3-state non-inverting outputs for bus-oriented applications
Common 3-state output enable input
Multiple package options
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
- JESD8C (2.7 V to 3.6 V)
- JESD7A (2.0 V to 6.0 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
DHVQFN package with Side-Wettable Flanks enabling Automated Optical Inspection (AOI) of solder joints
參數(shù)類(lèi)型
| 型號(hào) | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74HC573PW-Q100 | 2.0?-?6.0 | CMOS | ± 7.8 | 14 | 8 | low | -40~125 | 100 | 4.6 | 44.9 | TSSOP20 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
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封裝
| 型號(hào) | 可訂購(gòu)的器件編號(hào)，（訂購(gòu)碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74HC573PW-Q100 | 74HC573PW-Q100,118 (935298865118) |
Active | HC573 |
TSSOP20 (SOT360-1) |
SOT360-1 |
SSOP-TSSOP-VSO-WAVE
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SOT360-1_118 |
環(huán)境信息
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74HC573PW-Q100 | 74HC573PW-Q100,118 | 74HC573PW-Q100 |
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文檔 (11)
| 文件名稱(chēng) | 標(biāo)題 | 類(lèi)型 | 日期 |
|---|---|---|---|
| 74HC_HCT573_Q100 | Octal D-type transparent latch; 3-state | Data sheet | 2024-08-05 |
| AN11044 | Pin FMEA 74HC/74HCT family | Application note | 2019-01-09 |
| SOT360-1 | 3D model for products with SOT360-1 package | Design support | 2020-01-22 |
| hc573 | 74HC573 IBIS model | IBIS model | 2020-12-07 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP20_SOT360-1_mk | plastic, thin shrink small outline package; 20 leads; 0.65 mm pitch; 6.5 mm x 4.4 mm x 1.1 mm body | Marcom graphics | 2017-01-28 |
| SOT360-1 | plastic, thin shrink small outline package; 20 leads; 0.65 mm pitch; 6.5 mm x 4.4 mm x 1.2 mm body | Package information | 2024-11-15 |
| SOT360-1_118 | TSSOP20; Reel pack for SMD, 13''; Q1/T1 product orientation | Packing information | 2023-08-30 |
| 74HC573PW-Q100_Nexperia_Product_Reliability | 74HC573PW-Q100 Nexperia Product Reliability | Quality document | 2024-06-16 |
| HCT_USER_GUIDE | HC/T User Guide | User manual | 1997-10-31 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
支持
如果您需要設(shè)計(jì)/技術(shù)支持，請(qǐng)告知我們并填寫(xiě) 應(yīng)答表 我們會(huì)盡快回復(fù)您。
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
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訂購(gòu)、定價(jià)與供貨
| 型號(hào) | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線(xiàn)購(gòu)買(mǎi) |
|---|---|---|---|---|---|---|
| 74HC573PW-Q100 | 74HC573PW-Q100,118 | 935298865118 | Active | SOT360-1_118 | 2,500 | 訂單產(chǎn)品 |
樣品
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74HC573PW-Q100
Octal D-type transparent latch; 3-state
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