74AUP1G175GW-Q100

Low-power D-type flip-flop with reset; positive-edge trigger

Automotive qualified

The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. A LOW on MR causes the flip-flop and output to be reset to LOW. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

Automotive product qualification in accordance with AEC-Q100 (Grade 1)
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 0.8 V to 3.6 V
CMOS low power dissipation
High noise immunity
Complies with JEDEC standards:
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8C (2.7 V to 3.6 V)
Low static power consumption; I_CC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Overvoltage tolerant inputs to 3.6 V
Low noise overshoot and undershoot < 10 % of V_CC
I_OFF circuitry provides partial Power-down mode operation
ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

參數(shù)類型

型號	V_CC (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	Power dissipation considerations	T_amb (°C)	Package name
74AUP1G175GW-Q100	0.8?-?3.6	CMOS	± 1.9	7.4	70	ultra low	-40~125	TSSOP6

PCB Symbol, Footprint and 3D Model

Model Name	描述

封裝

型號	可訂購的器件編號，（訂購碼(12NC)）	狀態(tài)	標(biāo)示	封裝	外形圖	回流焊/波峰焊	包裝
74AUP1G175GW-Q100	74AUP1G175GW-Q100H (935300511125)	Active	aT	TSSOP6 (SOT363-2)	SOT363-2		SOT363-2_125

環(huán)境信息

型號	可訂購的器件編號	化學(xué)成分	RoHS	RHF指示符
74AUP1G175GW-Q100	74AUP1G175GW-Q100H	74AUP1G175GW-Q100

品質(zhì)及可靠性免責(zé)聲明

Series

文檔 (9)

文件名稱	標(biāo)題	類型	日期
74AUP1G175_Q100	Low-power D-type flip-flop with reset; positive-edge trigger	Data sheet	2023-08-03
AN10161	PicoGate Logic footprints	Application note	2002-10-29
AN11052	Pin FMEA for AUP family	Application note	2019-01-09
SOT363-2	3D model for products with SOT363-2 package	Design support	2023-02-02
aup1g175	aup1g175 IBIS model	IBIS model	2014-12-21
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Leaflet	2019-04-12
SOT363-2	plastic thin shrink small outline package; 6 leads; body width 1.25 mm	Package information	2022-11-21
SOT363-2_125	TSSOP6 ; Reel pack for SMD, 7"; Q3/T4 product orientation	Packing information	2022-11-04
74AUP1G175GW-Q100_Nexperia_Product_Reliability	74AUP1G175GW-Q100 Nexperia Product Reliability	Quality document	2024-06-16

支持

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模型

文件名稱	標(biāo)題	類型	日期
aup1g175	aup1g175 IBIS model	IBIS model	2014-12-21
SOT363-2	3D model for products with SOT363-2 package	Design support	2023-02-02

PCB Symbol, Footprint and 3D Model

Model Name	描述

訂購、定價(jià)與供貨

型號	Orderable part number	Ordering code (12NC)	狀態(tài)	包裝	Packing Quantity	在線購買
74AUP1G175GW-Q100	74AUP1G175GW-Q100H	935300511125	Active	SOT363-2_125	3,000	訂單產(chǎn)品

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How does it work?

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