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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調(diào)節(jié)ESD保護

MOSFET

氮化鎵場效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應(yīng)用認證產(chǎn)品(AEC-Q100/Q101)

74LVC574ADB

Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

The 74LVC574A is an 8?-?bit positive?-?edge triggered D?-?type flip?-?flop with 3?-?state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip?-?flops will store the state of their individual D?-?inputs that meet the set?-?up and hold time requirements on the LOW?-?to?-?HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high?-?impedance OFF?-?state. Operation of the OE input does not affect the state of the flip?-?flops. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt?-?trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

此產(chǎn)品已停產(chǎn)

Features and benefits

  • Wide supply voltage range from 1.2 to 3.6 V

  • CMOS low power consumption

  • Direct interface with TTL levels

  • Overvoltage tolerant inputs to 5.5 V

  • High-impedance when VCC = 0 V

  • 8-bit positive edge-triggered register

  • Independent register and 3-state buffer operation

  • Flow-through pin-out architecture

  • IOFF circuitry provides partial Power-down mode operation

  • Complies with JEDEC standard:

    • JESD8-7A (1.65 V to 1.95 V)

    • JESD8-5A (2.3 V to 2.7 V)

    • JESD8-C/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

參數(shù)類型

型號 Package name
74LVC574ADB SSOP20

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

下表中的所有產(chǎn)品型號均已停產(chǎn) 。

型號 可訂購的器件編號,(訂購碼(12NC)) 狀態(tài) 標示 封裝 外形圖 回流焊/波峰焊 包裝
74LVC574ADB 74LVC574ADB,112
(935219040112)
Obsolete LVC574A SOT339-1
SSOP20
(SOT339-1)
SOT339-1 SSOP-TSSOP-VSO-WAVE
暫無信息
74LVC574ADB,118
(935219040118)
Obsolete LVC574A SOT339-1_118

環(huán)境信息

下表中的所有產(chǎn)品型號均已停產(chǎn) 。

型號 可訂購的器件編號 化學(xué)成分 RoHS RHF指示符
74LVC574ADB 74LVC574ADB,112 74LVC574ADB rohs rhf rhf
74LVC574ADB 74LVC574ADB,118 74LVC574ADB rohs rhf rhf
品質(zhì)及可靠性免責(zé)聲明

文檔 (9)

文件名稱 標題 類型 日期
74LVC574A Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state Data sheet 2023-11-10
AN11009 Pin FMEA for LVC family Application note 2019-01-09
AN263 Power considerations when using CMOS and BiCMOS logic devices Application note 2023-02-07
AN90063 Questions about package outline drawings Application note 2025-03-12
lvc574a lvc574a IBIS model IBIS model 2013-04-09
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT339-1 plastic, shrink small outline package; 20 leads; 0.65 mm pitch; 7.2 mm x 5.3 mm x 2 mm body Package information 2020-04-21
lvc lvc Spice model SPICE model 2013-05-07
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

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Longevity

The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.


模型

文件名稱 標題 類型 日期
lvc574a lvc574a IBIS model IBIS model 2013-04-09
lvc lvc Spice model SPICE model 2013-05-07

PCB Symbol, Footprint and 3D Model

Model Name 描述

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

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