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Click here for more information74ALVT16821DL
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
The 74ALVT16821 is a 20-bit positive-edge triggered D-type flip-flop with 3-state outputs.
The device can be used as two 10-bit flip-flops or one 20-bit flip-flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 10-bits. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs
Features and benefits
Wide supply voltage range from 2.3 V to 3.6 V
Overvoltage tolerant inputs to 5.5 V
20-bit positive-edge triggered register
BiCMOS high speed and output drive
Direct interface with TTL levels
Bus hold on data inputs
No bus current loading when output is tied to 5 V bus
Power-up 3-state
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 500 mA per JESD 78 Class II Level B
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ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to 85 °C
參數(shù)類型
| 型號 | Package name |
|---|---|
| 74ALVT16821DL | SSOP56 |
封裝
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74ALVT16821DL | 74ALVT16821DL,112 (935210000112) |
Obsolete | ALVT16821 Standard Procedure Standard Procedure |
SSOP56 (SOT371-1) |
SOT371-1 |
SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE |
暫無信息 |
| 74ALVT16821DL,118 (935210000118) |
Obsolete | ALVT16821 Standard Procedure Standard Procedure | 暫無信息 | ||||
| 74ALVT16821DL,512 (935210000512) |
Obsolete | ALVT16821 Standard Procedure Standard Procedure | 暫無信息 | ||||
| 74ALVT16821DL,518 (935210000518) |
Obsolete | ALVT16821 Standard Procedure Standard Procedure | 暫無信息 |
環(huán)境信息
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號 | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74ALVT16821DL | 74ALVT16821DL,112 | 74ALVT16821DL |
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| 74ALVT16821DL | 74ALVT16821DL,118 | 74ALVT16821DL |
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| 74ALVT16821DL | 74ALVT16821DL,512 | 74ALVT16821DL |
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| 74ALVT16821DL | 74ALVT16821DL,518 | 74ALVT16821DL |
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Series
文檔 (8)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74ALVT16821 | 20-bit bus interface D-type flip-flop; positive-edge trigger; 3?-?state | Data sheet | 2024-06-25 |
| AN90063 | Questions about package outline drawings | Application note | 2025-03-12 |
| alvt16821 | alvt16821 IBIS model | IBIS model | 2013-04-08 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| SOT371-1 | plastic, shrink small outline package; 56 leads; 0.635 mm pitch; 18.45 mm x 7.5 mm x 2.8 mm body | Package information | 2020-04-21 |
| SSOP-TSSOP-VSO-REFLOW | Footprint for reflow soldering | Reflow soldering | 2009-10-08 |
| alvt16 | alvt16 Spice model | SPICE model | 2013-05-07 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
Longevity
The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.
How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74ALVT16821DL
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
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